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-- Company: 
-- Engineer:
--
-- Create Date:   18:47:24 11/06/2010
-- Design Name:   
-- Module Name:   C:/ADAM/Testdeconfmode.vhd
-- Project Name:  ADAM
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Gateway
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Testdeconfmode IS
END Testdeconfmode;
 
ARCHITECTURE behavior OF Testdeconfmode IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Gateway
    PORT(
         tdi : IN  std_logic;
         clk : IN  std_logic;
         shift : IN  std_logic;
         update : IN  std_logic;
         reset : IN  std_logic;
         wsoi : IN  std_logic;
         sel : OUT  std_logic;
         wsio : OUT  std_logic;
         tdo : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal tdi : std_logic := '0';
   signal clk : std_logic := '0';
   signal shift : std_logic := '0';
   signal update : std_logic := '0';
   signal reset : std_logic := '0';
   signal wsoi : std_logic := '0';

 	--Outputs
   signal sel : std_logic;
   signal wsio : std_logic;
   signal tdo : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Gateway PORT MAP (
          tdi => tdi,
          clk => clk,
          shift => shift,
          update => update,
          reset => reset,
          wsoi => wsoi,
          sel => sel,
          wsio => wsio,
          tdo => tdo
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;		
      reset <= '1';
      wait for 1*clk_period;
      reset <= '0';
      tdi <= '1';
	   shift <= '1';
		wait for 2*clk_period;
		shift <= '0';
		update <= '1';
		wait for 2*clk_period;
		update <= '0';
      wait for 2*clk_period;
      tdi <= '0';
		reset <= '1';
      wait for 1*clk_period;
		reset <= '0';
      tdi <= '1';
		shift <= '1';
      -- insert stimulus here 

      wait;
   end process;

END;
